1. Field of the Invention
The present invention relates to memory circuits, and more particularly to synchronous static random access memories (SRAMs) capable of transferring two data items per clock cycle and 100% bus utilization.
2. Description of Related Art
Asynchronous SRAMs have no input or output registers. Accessing an asynchronous SRAM is slow because the address and control signals (and the write data in case of a write operation) presented to the SRAM can not be changed for the duration of the SRAM access.
Synchronous SRAMs eliminate the requirement to hold the SRAM input signals (address, control, and data) during read or write operations by including clocked registers for storing the address, control, and read and write data. The set-up and hold times for the registers are typically much shorter than the time to access the memory array of the SRAM. This significantly reduces the SRAM's cycle time as viewed at the pins of the device, and thus the frequency of the system clock is increased.
The input and output registers however, cause two clock cycles of latency in the relation between the read address and read data, and no latency between the write address and write data (i.e., the address is clocked in and the data is clocked out in two consecutive clock cycles for a read, and the address and data are clocked in the same clock cycle for a write). This latency difference between read and write operations causes the address bus to remain idle for two clock cycles when a read cycle is followed by a write cycle, and causes the data bus to remain idle for two clock cycles when a write cycle is followed by a read cycle (i.e., bus turnaround). The idle cycles reduce the system data bandwidth.
Late write SRAMs partially correct the latency problem. In a late write SRAM, the number of idle cycles in a bus turnaround is reduced from two clock cycles to one by introducing one clock cycle of latency in the write. Zero bus turnaround (ZBT) synchronous SRAMs developed by Integrated Device Technology Inc. (U.S. Pat. No. 5,828,606, issued Oct. 27, 1998) eliminate idle cycles in a bus turn around by causing read and write operations to have the same clock cycle latency of two, and thus achieve 100% bus utilization. The two clock cycles of latency are however undesirable. Fewer cycles of latency, e.g., one, provide faster data availability and potentially faster and easier system design. (The ZBT SRAM latency can be reduced to one clock cycle, but only if no registers are provided on the SRAM output. This is undesirable because it increases the minimum cycle time.)
In all of the above SRAMs, at most one data item is transferred per clock cycle in either a read or a write operation. Double data rate (DDR) SRAMs transfer data into or out of the device on both the rising and falling clock edges, thus doubling the data transfer rate without increasing the clock frequency. One such device is the DDR late-write SRAM known as Claymore or MSUG-2 developed by a private consortium known as the Motorola Semiconductor Users Group (MSUG). This device was designed for high performance workstation level 2 cache operating in a point-to-point environment with data rates in excess of 500 MHz. While the Claymore device meets the needs for increased bandwidth in high performance communications applications, the lost clock cycle in every bus turn around (associated with every late write device) results in inefficient use of the address and data buses.
Thus, there is a need for a synchronous DDR SRAM capable of 100% bus utilization with fewer clock cycles of latency than the ZBT SRAM.